1. Field of the Invention
This invention relates to the field of data processing. More particularly, this invention relates to data processing systems including a floating point addition circuit.
2. Description of the Prior Art
It is known to provide data processing systems including a floating point addition circuit. This circuit may be provided individually or together with a multiplier circuit. In the case of a system having an adder circuit and a multiplier circuit, this may be in the form of a multiply-accumulate circuit. In order to improve the performance of such floating point circuits it is known to arrange them in the form of a pipelined system. One of the stages in such pipelined systems is typically normalization and rounding. The rounding step involves both determining that rounding should or should not take place together with incrementing the result if rounding is required. An example of such a system is described in U.S. Pat. No. 4,999,802.
A constant aim within data processing systems is to increase the operating speed. One way of helping to achieve this is to reduce the number of processing cycles needed to perform a desired operation, such as a floating point addition. In a pipelined system, reducing the number of pipeline stages through which an operation must pass before its result is available for use is strongly advantageous as it allows any subsequent processing operation depends upon that result to start to be initiated sooner. Sequences of dependent operations such as the above are relatively common in performance critical fields such as real-time DSP.